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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4059B LSI Programmable divide-by-n counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Programmable divide-by-n counter DESCRIPTION The HEF4059B is a divide-by-n counter which can be programmed to divide an input frequency by any number n from 3 to 15 999. The output signal is a one clock-cycle HEF4059B LSI wide pulse and occurs at a rate equal to the input frequency divided by n. The single output (O) has TTL drive capability. The down counter is preset by means of 16 jam inputs (J1 to J16); continued on next page. Fig.1 Functional block diagram. PINNING CP Ka, Kb, Kc J1 to J16 EL O clock input mode select inputs programmable jam inputs (BCD) latch enable input divide-by-n output HEF4059BP(N): 24-lead DIL; plastic (SOT101-1) Fig.2 Pinning diagram. HEF4059BD(F): HEF4059BT(D): FAMILY DATA, IDD LIMITS category LSI See Family Specifications 24-lead DIL; ceramic (cerdip) (SOT94) 24-lead SO; plastic (SOT137-1) ( ): Package Designator North America January 1995 2 Philips Semiconductors Product specification Programmable divide-by-n counter The three mode selection inputs Ka, Kb and Kc determine the modulus (`divide-by' number) of the first and last counting sections in accordance with Table 1. Every time the first (fastest) counting section goes through one cycle, it reduces, by 1, the number that has been preset (jammed) into the three decades of the intermediate counting section and into the last counting section (which consists of flip-flops that are not needed for operating the first counting section). For example, in the / 2 mode, only one flip-flop is needed in the first counting section. Therefore the last (5th) counting section has three flip-flops that can be preset to a maximum count of seven with a place value of thousands. This counting mode is selected when Ka, Kb and Kc are set to HIGH. In this case input J1 is used to preset the first counting section and J2 to J4 are used to preset the last (5th) counting section. If / 10 mode is desired for the first section, Ka is set HIGH, Kb to HIGH and Kc to LOW. The jam inputs J1 to J4 are used to preset the first counting section and there is no last counting section. The intermediate counting section consists of three cascaded BCD decade (/ 10) counters, presettable by means of the jam inputs J5 to J16. When clock pulses are applied to the clock input after a 4 J1 L J2 L J3 H 1 J4 H J5 H J6 L 5 J7 H J8 L J9 H J10 L HEF4059B LSI number n has been preset into the counter, the counter counts down until the DETECTION circuit detects the zero state. At this time the PRESET ENABLE circuit is enabled to preset again the number n into the counter and to produce an output pulse. The preset of the counter to a desired / n is achieved as follows: n = (MODE*) (1000 x decade 5 preset + 100 x decade 4 preset + 10 x decade 3 preset + 1 x decade 2 preset) + decade 1 preset. * MODE = first counting section divider (10, 8, 5, 4 or 2). To calculate preset values for any n count, divide the n count by the selected mode. The resultant is the corresponding preset values of the 5th to the 2nd decade with the remainder being equal to the 1st decade value. n preset value = --------------- . mode If n = 8479, and the selected mode = 5, the preset value = 8479 / 5 = 1695 with a remainder of 4, thus the jam inputs must be set as follows: 9 J11 L J12 H J13 L J14 H 6 J15 H J16 L The mode select inputs permit frequency-synthesizer channel separations of 10, 12,5, 20, 25 and 50 parts. These inputs set the maximum value of n at 9999 (when the first counting section divides by 5 or 10) or at 15 999 (when the first counting section divides by 8, 4 or 2). The three decades of the intermediate counting section can be preset to a binary 15 instead of a binary 9. In this case the first cycle of a counter consists of 15 count pulses, the next cycles consisting of 10 count pulses. Thus the place value of the three decades are still 1, 10 and 100. For example, in the / 8 mode, the number from which the intermediate counting section begins to count-down can be preset to: 3rd 1st decade: decade: 1500 150 15 1665 2nd decade: The last counting section can be preset to a maximum of 1, with a place value of 1000. The total of these numbers (2665) times 8 equals 21 320. The first counting section can be preset to a maximum of 7. Therefore, 21 327 is the maximum possible count in the / 8 mode. The highest count of the various modes is shown in Table 1, in the column entitled `extended counter range'. Control inputs Kb and Kc can be used to initiate and lock the counter in the `master preset' mode. In this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that mode as long as Kb and Kc both remain LOW. The counter begins to run down from the preset state when a counting mode other than the `master preset' mode is selected. Whenever the `master preset' mode is used, control signals Kb = L and Kc = L must be applied for at least 3 full clock pulses. After the master preset mode inputs have been changed to one of the counting modes, the next positive-going clock transition changes an internal flip-flop so that the count-down can begin at the second positive-going clock transition. Thus, after a `master preset' mode, there is always one extra count before the output goes HIGH. January 1995 3 Philips Semiconductors Product specification Programmable divide-by-n counter Figure 3 illustrates the operation of the counter in mode / 8 starting from the preset state 3. HEF4059B LSI CP INPUT Kc INPUT (Ka, Kb = LOW) internal state of counter O OUTPUT Fig.3 Total count of 3. If the `master preset' mode is started two clock cycles or less before an output pulse, the output pulse will appear at the time due. If the `master preset' mode is not used the counter is preset in accordance with the `jam inputs when the output pulse appears. A HIGH level at the latch enable input (EL) will cause the counter output to go HIGH once an output pulse occurs, and remain in the HIGH state until EL input returns to LOW. If the EL input is LOW, the output pulse will remain HIGH for only one cycle of the clock input signal. When Ka = L, Kb = H, Kc = L and EL = L, the counter operates in the `preset inhibit' mode, with which the dividend of the counter is fixed to 10 000, independent of the state of the jam inputs. When in the same state of mode select inputs EL = H, the counter operates in the normal / 10 mode, however, without the latch operation at the output. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. January 1995 4 Philips Semiconductors Product specification Programmable divide-by-n counter FUNCTION TABLE LATCH ENABLE INPUT MODE SELECT INPUTS FIRST COUNTING SECTION DECADE 1 MAX. PRESET STATE JAM INPUTS USED LAST COUNTING SECTION DECADE 5 DIVIDE BY MAX. PRESET STATE JAM INPUTS USED COUNTER RANGE HEF4059B LSI OPERATION LE Ka Kb Kc MODE BCD MAX. BINARY MAX. H H H H H L L L L L H L X Note H L H L H H L H L H L L X H H L L H H H L L H H H L H H H H L H H H H L L L L 2 4 5 8 10 2 4 5 8 10 10 1 3 4 7 9 1 3 4 7 9 9 J1 J1J2 J1J2J3 J1J2J3 J1 J1J2 J1J2J3 J1J2J3 8 4 2 2 8 4 2 2 7 3 1 1 0 7 3 1 1 0 0 J2J3J4 J3J4 J4 J4 - J2J3J4 J3J4 J4 J4 - - 15 999 17 331 15 999 18 663 9 999 13 329 15 999 21 327 9 999 16 659 15 999 17 331 15 999 18 663 9 999 13 329 15 999 21 327 9 999 16 659 9 999 16 659 fixed - 10 000 - - divide-by-10 000 mode divide-by-n mode timer mode J1J2J3J4 1 J1J2J3J4 1 J1J2J3J4 1 preset inhibited master preset preset inhibited master preset master preset mode 1. It is recommended that the device is in the master preset mode (Kb = Kc = logic 0) in order to correctly initialize the device prior to start up. 2. H = HIGH voltage level L = LOW voltage level X = don't care DC CHARACTERISTICS VSS = 0 V VDD V Output (sink) current LOW Output (source) current HIGH Output (source) current HIGH 5 -IOH 2,4 2 1,6 mA VO = 2,5 V; VI = 0 or 5V 4,75 10 15 5 10 15 -IOH IOL Tamb (C) SYMBOL -40 MIN. 2,7 9,5 24 0,8 2,4 8,4 + 25 MIN. 2,3 8 20 0,7 2 7 + 85 MIN. 1,8 6,3 16 0,5 1,6 5,6 UNIT mA mA mA mA mA mA VO = VO = VO = VO = VO = 0,4 V; VI = 0 or 4,75 V 0,5 V; VI = 0 or 10 V 1,5 V; VI = 0 or 15 V 4,6 V; VI = 0 or 5 V 9,5 V; VI = 0 or 10 V VO = 13,5 V; VI = 0 or 15 V January 1995 5 Philips Semiconductors Product specification Programmable divide-by-n counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P); n = 3 n = 1000 5 10 15 5 10 15 TYPICAL FORMULA FOR P (W) 1 100 fi + (foCL) x VDD2 5 500 fi + (foCL) x VDD2 15 000 fi + (foCL) x VDD2 500 fi + (foCL) x VDD2 3 500 fi + (foCL) x VDD2 9 000 fi + (foCL) x VDD2 where HEF4059B LSI fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP O HIGH to LOW LOW to HIGH Output transition times HIGH to LOW 5 10 15 5 10 15 5 10 15 5 LOW to HIGH Maximum clock pulse frequency 10 15 5 10 15 fmax 3,5 7,5 10,0 tTLH tTHL tPLH tPHL SYMBOL MIN. TYP. 90 45 35 100 50 40 30 15 10 45 25 16 7 15 20 MAX. 180 90 70 200 100 80 60 30 20 90 50 32 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz TYPICAL EXTRAPOLATION FORMULA 78 ns + (0,25 ns/pF) CL 40 ns + (0,10 ns/pF) CL 32 ns + (0,07 ns/pF) CL 76 ns + (0,48 ns/pF) CL 40 ns + (0,20 ns/pF) CL 33 ns + (0,15 ns/pF) CL 10 ns + (0,40 ns/pF) CL 6 ns + (0,18 ns/pF) CL 4 ns + (0,13 ns/pF) CL 10 ns + (0,70 ns/pF) CL 9 ns + (0,33 ns/pF) CL 5 ns + (0,23 ns/pF) CL January 1995 6 |
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